[Hpcresilience] 2nd Call for Papers, SELSE 2019: March 27--28, 2019 in Stanford, Palo Alto, CA, USA

Michael Sullivan misullivan at nvidia.com
Wed Dec 19 15:14:38 MST 2018

The 15th IEEE Workshop on Silicon Errors in Logic - System Effects

SELSE 2019 (http://www.selse.org<http://www.selse.org/>)

March 27 - March 28, 2019, Stanford, Palo Alto, CA, USA

Important dates:

  *   Paper Registration (mandatory):

January 7, 2019

  *   Paper Submission (for registered papers):

January 11, 2019

  *   Author Notification:

February 15, 2019

  *   Early Registration:

February 22, 2019

  *   Camera-Ready Submission:

March 8, 2019

The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching, both in safety-critical aerospace and automotive applications and also for large scale servers and high performance applications.

The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. SELSE solicits papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also welcome.

We are happy to announce that selected SELSE papers will be included in the "Best of SELSE" session at IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2019. These papers will be selected based on the importance of the topic, technical contributions, quality of results, and authors' agreement to travel to present at DSN in Portland, Oregon on June 24 - 27, 2019.


Key areas of interest include (but are not limited to):

  *   Error rates and trends in current and emerging technologies, including experimental failure data and the reliability characterization of deployed systems.
  *   New error mitigation techniques, robust software frameworks, and error handling protocols for resilient system design.
  *   Case studies analyzing the overhead, effectiveness, and design complexity of error mitigation techniques.
  *   Resilience characterization and strategies for machine learning applications, including autonomous vehicles.
  *   Resilience in new architectures, for example accelerator-rich systems and inexact or approximate computing.
  *   The design of resilient systems for space exploration.
  *   The interplay between system security issues and reliability.

Submission Guidelines

Additional information and guidelines for submission are available at http://www.selse.org<http://www.selse.org/>.  Submissions and final papers should be PDF files following the IEEE two-column transactions format with six or fewer printed pages of text; the bibliography does not count against this page limit. Papers are not published through IEEE/ACM nor archived in the digital libraries---however, they are distributed to attendees of the workshop.

Organizing Committee

General Co-Chairs

Laura Monroe, LANL
John Daly, LPS
Siva Hari, NVIDIA (Emeritus)

Program Co-Chairs

Michael Sullivan, NVIDIA
Puneet Gupta, UCLA
Paolo Rech, UFRGS (Emeritus)

Finance Co-Chairs

Steven Raasch, AMD

Sarah Michalak, LANL

Registration Chair

Karthik Swaminathan, IBM

Local Arrangements Chair

Saurabh Hukerikar, NVIDIA

Publicity Co-Chairs

Michael Sullivan, NVIDIA (North America)
Tiago Balen, UFRGS (South America)
Stefano Di Carlo, PoliTo (Europe)
Yi-Pin Fang, TSMC (Asia)

Bay Area Industry Liaisons

Shahrzad Mirkhani, Bigstream
Mark Gottscho, Google


Vanessa Job, LANL/UNM

Advisors to the Committee

Sarah Michalak, LANL
Alan Wood, Oracle
Vilas Sridharan, AMD

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