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<body lang="EN-US" link="blue" vlink="purple">
<div class="WordSection1">
<p style="margin:0in;margin-bottom:.0001pt"><b><span style="font-size:12.0pt;color:black">The 15th IEEE Workshop on Silicon Errors in Logic – System Effects</span></b><o:p></o:p></p>
<p style="margin:0in;margin-bottom:.0001pt"><b><span style="font-size:12.0pt;color:black">SELSE 2019 (</span></b><a href="http://www.selse.org/"><span style="font-size:12.0pt;color:#0B4CB4">http://www.selse.org</span></a><b><span style="font-size:12.0pt;color:black">)</span></b><o:p></o:p></p>
<p style="margin:0in;margin-bottom:.0001pt"><span style="font-size:12.0pt;color:black">March 27 – March 28, 2019, Stanford, Palo Alto, CA, USA</span><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<h3 style="mso-margin-top-alt:10.0pt;margin-right:0in;margin-bottom:4.0pt;margin-left:0in">
<span style="font-size:12.0pt;font-family:"Cambria",serif;color:black">Important dates:</span><o:p></o:p></h3>
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<li style="color:black;margin-top:0in;margin-bottom:0in;margin-bottom:.0001pt;mso-list:l3 level1 lfo1;vertical-align:baseline">
<b><span style="font-size:12.0pt">Paper Registration (mandatory): <o:p></o:p></span></b></li></ul>
</td>
<td valign="top" style="padding:.75pt .75pt .75pt .75pt">
<p style="margin:0in;margin-bottom:.0001pt"><b><span style="font-size:12.0pt;color:black">January 7, 2019</span></b><o:p></o:p></p>
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<li style="color:black;margin-top:0in;margin-bottom:0in;margin-bottom:.0001pt;mso-list:l4 level1 lfo2;vertical-align:baseline">
<b><span style="font-size:12.0pt">Paper Submission (for registered papers): <o:p></o:p></span></b></li></ul>
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<td valign="top" style="padding:.75pt .75pt .75pt .75pt">
<p style="margin:0in;margin-bottom:.0001pt"><b><span style="font-size:12.0pt;color:black">January 11, 2019</span></b><o:p></o:p></p>
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<li style="color:black;margin-top:0in;margin-bottom:0in;margin-bottom:.0001pt;mso-list:l1 level1 lfo3;vertical-align:baseline">
<b><span style="font-size:12.0pt">Author Notification: <o:p></o:p></span></b></li></ul>
</td>
<td valign="top" style="padding:.75pt .75pt .75pt .75pt">
<p style="margin:0in;margin-bottom:.0001pt"><b><span style="font-size:12.0pt;color:black">February 15, 2019</span></b><o:p></o:p></p>
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<li style="color:black;margin-top:0in;margin-bottom:0in;margin-bottom:.0001pt;mso-list:l0 level1 lfo4;vertical-align:baseline">
<b><span style="font-size:12.0pt">Early Registration:<o:p></o:p></span></b></li></ul>
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<td valign="top" style="padding:.75pt .75pt .75pt .75pt">
<p style="margin:0in;margin-bottom:.0001pt"><b><span style="font-size:12.0pt;color:black">February 22, 2019</span></b><o:p></o:p></p>
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<b><span style="font-size:12.0pt">Camera-Ready Submission: <o:p></o:p></span></b></li></ul>
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<p style="margin:0in;margin-bottom:.0001pt"><b><span style="font-size:12.0pt;color:black">March 8, 2019</span></b><o:p></o:p></p>
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<span style="font-size:12.0pt;color:black">The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor
aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching, both in safety-critical aerospace and automotive applications and also for large scale servers and high performance applications.
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<span style="font-size:12.0pt;color:black">The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. SELSE solicits papers that address the system-level effects of errors from a variety of perspectives:
architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also welcome.</span><o:p></o:p></p>
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<span style="font-size:12.0pt;color:black">We are happy to announce that selected SELSE papers will be included in the “Best of SELSE” session at IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2019. These papers will be selected
based on the importance of the topic, technical contributions, quality of results, and authors’ agreement to travel to present at DSN in Portland, Oregon on June 24 – 27, 2019.</span><o:p></o:p></p>
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<span style="font-size:12.0pt;font-family:"Cambria",serif;color:black">Areas</span><o:p></o:p></h3>
<p style="margin:0in;margin-bottom:.0001pt;text-align:justify"><span style="font-size:12.0pt;color:black">Key areas of interest include (but are not limited to):</span><o:p></o:p></p>
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<span style="font-size:12.0pt">Error rates and trends in current and emerging technologies, including experimental failure data and the reliability characterization of deployed systems.</span><span style="font-size:12.0pt;font-family:"Arial",sans-serif"><o:p></o:p></span></li><li style="color:black;margin-top:0in;margin-bottom:0in;margin-bottom:.0001pt;text-align:justify;mso-list:l5 level1 lfo6;vertical-align:baseline">
<span style="font-size:12.0pt">New error mitigation techniques, robust software frameworks, and error handling protocols for resilient system design.</span><span style="font-size:12.0pt;font-family:"Arial",sans-serif"><o:p></o:p></span></li><li style="color:black;margin-top:0in;margin-bottom:0in;margin-bottom:.0001pt;text-align:justify;mso-list:l5 level1 lfo6;vertical-align:baseline">
<span style="font-size:12.0pt">Case studies analyzing the overhead, effectiveness, and design complexity of error mitigation techniques.</span><span style="font-size:12.0pt;font-family:"Arial",sans-serif"><o:p></o:p></span></li><li style="color:black;margin-top:0in;margin-bottom:0in;margin-bottom:.0001pt;text-align:justify;mso-list:l5 level1 lfo6;vertical-align:baseline">
<span style="font-size:12.0pt">Resilience characterization and strategies for machine learning applications, including autonomous vehicles.<o:p></o:p></span></li><li style="color:black;margin-top:0in;margin-bottom:0in;margin-bottom:.0001pt;text-align:justify;mso-list:l5 level1 lfo6;vertical-align:baseline">
<span style="font-size:12.0pt">Resilience in new architectures, for example accelerator-rich systems and inexact or approximate computing.<o:p></o:p></span></li><li style="color:black;margin-top:0in;margin-bottom:0in;margin-bottom:.0001pt;text-align:justify;mso-list:l5 level1 lfo6;vertical-align:baseline">
<span style="font-size:12.0pt">The design of resilient systems for space exploration.<o:p></o:p></span></li><li style="color:black;margin-top:0in;margin-bottom:0in;margin-bottom:.0001pt;text-align:justify;mso-list:l5 level1 lfo6;vertical-align:baseline">
<span style="font-size:12.0pt">The interplay between system security issues and reliability.<o:p></o:p></span></li></ul>
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<span style="font-size:12.0pt;font-family:"Cambria",serif;color:black">Submission Guidelines</span><o:p></o:p></h3>
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<span style="font-size:12.0pt;color:black">Additional information and guidelines for submission are available at
</span><a href="http://www.selse.org/"><span style="font-size:12.0pt;color:#0B4CB4">http://www.selse.org</span></a><span style="font-size:12.0pt;color:black">. Submissions and final papers should be PDF files following the IEEE two-column transactions format
with six or fewer printed pages of text; the bibliography does not count against this page limit. Papers are not published through IEEE/ACM nor archived in the digital libraries---however, they are distributed to attendees of the workshop.</span><o:p></o:p></p>
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<span style="font-size:12.0pt;font-family:"Cambria",serif;color:black">Organizing Committee</span><o:p></o:p></h3>
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<p style="margin:0in;margin-bottom:.0001pt"><span style="font-size:12.0pt;color:black">General Co-Chairs</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt"><span style="font-size:12.0pt;color:black">Laura Monroe, LANL<br>
John Daly, LPS<br>
Siva Hari, NVIDIA (Emeritus)</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt"><span style="font-size:12.0pt;color:black">Program Co-Chairs</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt"><span style="font-size:12.0pt;color:black">Michael Sullivan, NVIDIA<br>
Puneet Gupta, UCLA<br>
Paolo Rech, UFRGS (Emeritus)</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt"><span style="font-size:12.0pt;color:black">Finance Co-Chairs</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt"><span style="font-size:12.0pt;color:black">Steven Raasch, AMD</span><o:p></o:p></p>
<p style="margin:0in;margin-bottom:.0001pt"><span style="font-size:12.0pt;color:black">Sarah Michalak, LANL</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt;text-align:justify"><span style="font-size:12.0pt;color:black">Registration Chair</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt"><span style="font-size:12.0pt;color:black">Karthik Swaminathan, IBM</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt;text-align:justify"><span style="font-size:12.0pt;color:black">Local Arrangements Chair</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt"><span style="font-size:12.0pt;color:black">Saurabh Hukerikar, NVIDIA</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt;text-align:justify"><span style="font-size:12.0pt;color:black">Publicity Co-Chairs</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt"><span style="font-size:12.0pt;color:black">Michael Sullivan, NVIDIA (North America)<br>
Tiago Balen, UFRGS (South America)<br>
Stefano Di Carlo, PoliTo (Europe)<br>
Yi-Pin Fang, TSMC (Asia)</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt;text-align:justify"><span style="font-size:12.0pt;color:black">Bay Area Industry Liaisons</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt"><span style="font-size:12.0pt;color:black">Shahrzad Mirkhani, Bigstream<br>
Mark Gottscho, Google</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt"><span style="font-size:12.0pt;color:black">Webmaster</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt"><span style="font-size:12.0pt;color:black">Vanessa Job, LANL/UNM</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt;text-align:justify"><span style="font-size:12.0pt;color:black">Advisors to the Committee</span><o:p></o:p></p>
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<p style="margin:0in;margin-bottom:.0001pt"><span style="font-size:12.0pt;color:black">Sarah Michalak, LANL<br>
Alan Wood, Oracle<br>
Vilas Sridharan, AMD</span><o:p></o:p></p>
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