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<p class="MsoNormal"><b>The 12th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE 2016)<o:p></o:p></b></p>
<p class="MsoNormal">March 29 – 30, 2016 – Austin, TX, USA<o:p></o:p></p>
<p class="MsoNormal">Website: <a href="http://www.selse.org">http://www.selse.org</a><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><b>NEW! Special session at DSN for best SELSE papers!<o:p></o:p></b></p>
<p class="MsoNormal">There will be a special session at the 46th Annual IEEE/IFIP Conference on Dependable Systems and Networks (DSN) in Toulouse, France dedicated for the best papers of SELSE 2016. The selected SELSE papers will have the opportunity to be
presented in the special session and published in the DSN workshop proceedings.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><b>Important dates:<o:p></o:p></b></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l1 level1 lfo1"><![if !supportLists]><span style="font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Register an abstract: December 14, 2015<o:p></o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l1 level1 lfo1"><![if !supportLists]><span style="font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Paper submission: January 4, 2016
<o:p></o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l1 level1 lfo1"><![if !supportLists]><span style="font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Authors notification: February 23, 2016<o:p></o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l1 level1 lfo1"><![if !supportLists]><span style="font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Camera-ready submission: March 8, 2016<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the
effects of natural radiation. The system-level impact of these errors can be far-reaching. Growing concern about intermittent errors, unstable storage cells, and the effects of aging are influencing system design, and failures in memories account for a significant
fraction of costly product returns. Emerging logic and memory device technologies introduce several reliability challenges that need to be addressed to make these technologies viable. Additionally, reliability is a key issue for large-scale systems, such as
those in data centers and cloud computing infrastructure.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The SELSE workshop provides a forum for discussion of current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research directions. SELSE is soliciting
papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies are also solicited.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Key areas of interest are (but not limited to):<o:p></o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l0 level1 lfo2"><![if !supportLists]><span style="font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Technology trends and the impact on error rates.<o:p></o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l0 level1 lfo2"><![if !supportLists]><span style="font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>New error mitigation techniques.<o:p></o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l0 level1 lfo2"><![if !supportLists]><span style="font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Characterizing the overhead and design complexity of error mitigation techniques.<o:p></o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l0 level1 lfo2"><![if !supportLists]><span style="font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Case studies describing the tradeoff analysis for reliable systems.<o:p></o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l0 level1 lfo2"><![if !supportLists]><span style="font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Experimental data on failures in current and emerging technologies.<o:p></o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l0 level1 lfo2"><![if !supportLists]><span style="font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>System-level models: derating factors and validation of error models.<o:p></o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l0 level1 lfo2"><![if !supportLists]><span style="font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Error handling protocols (higher-level protocols for robust system design).<o:p></o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l0 level1 lfo2"><![if !supportLists]><span style="font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Characterization of reliability of systems deployed in the field and mitigation of issues.<o:p></o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l0 level1 lfo2"><![if !supportLists]><span style="font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Software-level impact of hardware failures.<o:p></o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l0 level1 lfo2"><![if !supportLists]><span style="font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Software frameworks for resilience.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Authors are requested to register to submit a paper by <b>December 14, 2015</b>. The paper submission deadline is
<b>January 4, 2016</b>. Papers will be considered for both oral and poster presentation, and all accepted submissions will be distributed to SELSE participants. Authors will be notified by
<b>February 23, 2016</b>. Final papers are due on <b>March 8, 2016</b>.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Additional information and guidelines for submission are available at
<a href="http://www.selse.org">http://www.selse.org</a>. Submissions and final papers should be in PDF following IEEE two-column transactions format that does not exceed six printed pages of text; the bibliography does not count against this page limit. Papers
are not made available through IEEE, and authors retain the copyright of their work. Authors may optionally choose to make their presentations available online at the workshop web site. Authors of papers selected for the DSN Best-of-SELSE session will have
the option to work with the DSN publications committee to prepare the camera-ready versions for the DSN workshop proceedings.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><b>Organizing Committee<o:p></o:p></b></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">General Chairs: Helia Naeimi, Intel<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:1.5in;text-indent:.5in">Dan Alexandrescu, iRoC<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Program Chairs: Sudhanva Gurumurthi, IBM/University of Virginia<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:1.5in;text-indent:.5in">Mattan Erez, The University of Texas at Austin<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Finance Chairs: Siva Hari, NVIDIA<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:1.5in;text-indent:.5in">Daniel Lowell, AMD<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Publicity Chairs: William H. Robinson, Vanderbilt University<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:1.5in;text-indent:.5in">Paolo Rech, UFRGS<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:1.5in;text-indent:.5in">Yiannakis Sazeides, University of Cyprus<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Documents Chairs: Mehdi Tahoori, Karlsruhe Institute of Technology<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:1.5in;text-indent:.5in">Mojtaba Ebrahimi, Karlsruhe Institute of Technology<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Austin Industry Liaison: Indrani Paul, AMD<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Webmaster: Marios Kleanthous, Mesoyios College
<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Local Arrangements Chair: Vijay Janapa Reddi, The University of Texas at Austin<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Advisors to the Committee: Sarah Michalak, LANL<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:1.5in;text-indent:.5in">Alan Wood, Oracle<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:1.5in;text-indent:.5in">Vilas Sridharan, AMD<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:1.5in;text-indent:.5in">Adrian Evans, iRoC<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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