[Hpcresilience] Call for Papers - SELSE 2016: March 29 – 30, 2016 - Austin, TX, USA

Robinson, William H william.h.robinson at Vanderbilt.Edu
Sat Oct 17 14:24:33 MDT 2015


The 12th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE 2016)
March 29 – 30, 2016 – Austin, TX, USA
Website: http://www.selse.org

NEW! Special session at DSN for best SELSE papers!
There will be a special session at the 46th Annual IEEE/IFIP Conference on Dependable Systems and Networks (DSN) in Toulouse, France dedicated for the best papers of SELSE 2016. The selected SELSE papers will have the opportunity to be presented in the special session and published in the DSN workshop proceedings.

Important dates:

·         Register an abstract:                       December 14, 2015

·         Paper submission:                           January 4, 2016

·         Authors notification:                      February 23, 2016

·         Camera-ready submission:          March 8, 2016

The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching. Growing concern about intermittent errors, unstable storage cells, and the effects of aging are influencing system design, and failures in memories account for a significant fraction of costly product returns. Emerging logic and memory device technologies introduce several reliability challenges that need to be addressed to make these technologies viable. Additionally, reliability is a key issue for large-scale systems, such as those in data centers and cloud computing infrastructure.

The SELSE workshop provides a forum for discussion of current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research directions. SELSE is soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies are also solicited.

Key areas of interest are (but not limited to):

·         Technology trends and the impact on error rates.

·         New error mitigation techniques.

·         Characterizing the overhead and design complexity of error mitigation techniques.

·         Case studies describing the tradeoff analysis for reliable systems.

·         Experimental data on failures in current and emerging technologies.

·         System-level models: derating factors and validation of error models.

·         Error handling protocols (higher-level protocols for robust system design).

·         Characterization of reliability of systems deployed in the field and mitigation of issues.

·         Software-level impact of hardware failures.

·         Software frameworks for resilience.

Authors are requested to register to submit a paper by December 14, 2015. The paper submission deadline is January 4, 2016. Papers will be considered for both oral and poster presentation, and all accepted submissions will be distributed to SELSE participants. Authors will be notified by February 23, 2016. Final papers are due on March 8, 2016.

Additional information and guidelines for submission are available at http://www.selse.org. Submissions and final papers should be in PDF following IEEE two-column transactions format that does not exceed six printed pages of text; the bibliography does not count against this page limit. Papers are not made available through IEEE, and authors retain the copyright of their work. Authors may optionally choose to make their presentations available online at the workshop web site. Authors of papers selected for the DSN Best-of-SELSE session will have the option to work with the DSN publications committee to prepare the camera-ready versions for the DSN workshop proceedings.

Organizing Committee

General Chairs:                                 Helia Naeimi, Intel
Dan Alexandrescu, iRoC

Program Chairs:                                Sudhanva Gurumurthi, IBM/University of Virginia
Mattan Erez, The University of Texas at Austin

Finance Chairs:                                  Siva Hari, NVIDIA
Daniel Lowell, AMD

Publicity Chairs:                                William H. Robinson, Vanderbilt University
Paolo Rech, UFRGS
Yiannakis Sazeides, University of Cyprus

Documents Chairs:                          Mehdi Tahoori, Karlsruhe Institute of Technology
Mojtaba Ebrahimi, Karlsruhe Institute of Technology

Austin Industry Liaison:                 Indrani Paul, AMD

Webmaster:                                       Marios Kleanthous, Mesoyios College

Local Arrangements Chair:           Vijay Janapa Reddi, The University of Texas at Austin

Advisors to the Committee:        Sarah Michalak, LANL
Alan Wood, Oracle
Vilas Sridharan, AMD
Adrian Evans, iRoC

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