[Hpcresilience] Update: Call for Papers - SELSE 2015: March 31 – April 1, 2015 - Austin, TX
Robinson, William H
william.h.robinson at Vanderbilt.Edu
Wed Dec 17 09:44:30 MST 2014
Workshop on Silicon Errors in Logic – System Effects (SELSE 2015)
March 31 – April 1, 2015 – Austin, TX
Confirmed keynote speakers include:
Rob Aitken, ARM
Pradip Bose, IBM
NOTE TO AUTHORS: The deadlines have been updated.
· Register an abstract: December 8, 2014 January 2, 2015
· Paper submission: December 15, 2014 January 2, 2015
· Authors notification: January 30, 2015 February 6, 2015
· Camera-ready submission: February 18, 2015 February 23, 2015
The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching. Growing concern about intermittent errors, unstable storage cells, and the effects of aging are influencing system design and failures in memories account for a significant fraction of costly product returns. Emerging logic and memory device technologies introduce several reliability challenges that need to be addressed to make these technologies viable. Finally, reliability is a key issue for large-scale systems, such as those in data centers. The SELSE workshop provides a forum for discussion of current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research directions (including nanotechnology). SELSE is soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies are also solicited.
Key areas of interest are (but not limited to):
• Technology trends and the impact on error rates.
• New error mitigation techniques.
• Characterizing the overhead and design complexity of error mitigation techniques.
• Case studies describing the tradeoffs analysis for reliable systems.
• Experimental silicon failure data.
• System-level models: derating factors and validation of error models.
• Error handling protocols (higher-level protocols for robust system design).
• Characterization of reliability of systems deployed in the field and mitigation of issues.
Authors are requested to register their paper and submit it for review by January 2, 2015. Papers will be considered for both oral and poster presentation, and all accepted submissions will be distributed to SELSE participants. Authors will be notified by February 6, 2015. Final papers are due on February 23, 2015.
Additional information and guidelines for submission are available at http://www.selse.org. Submissions and final papers should be in PDF following IEEE two-column conference proceedings format that does not exceed six printed pages. Papers are not made available through IEEE, and authors retain the copyright of their work. Authors may optionally choose to make their presentations available online at the workshop web site.
General Chairs: Sarah Michalak, Los Alamos National Laboratory
Helia Naeimi, Intel
Program Chairs: Dimitris Gizopoulos, University of Athens
Sudhanva Gurumurthi, AMD/University of Virginia
Finance Chairs: Dan Alexandrescu, iROC Technologies
Siva Hari, NVIDIA
Local Arrangements Chair: Vijay Janapa Reddi, UT-Austin
Publicity Chairs: Yi-Pin Fang, TSMC
Paolo Rech, UFRGS
William H. Robinson, Vanderbilt University
Yanos Sazeides, University of Cyprus
Austin Industry Liaison: Daniel Lowell, AMD
Documents Chair: Mehdi Tahoori, Karlsruhe Institute of Technology
Webmaster: Marios Kleanthous, Mesoyios College
Advisors to the Committee: Adrian Evans, iROC Technologies
Vilas Sridharan, AMD
Alan Wood, Oracle
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