[Hpcresilience] Call for Papers, SELSE 2018: April 3--April 4, 2018 in Boston, Massachusetts, USA

[Michael Sullivan]

The 14th IEEE Workshop on Silicon Errors in Logic - System Effects SELSE 2018 (http<http://www.selse.org/>://<http://www.selse.org/>www<http://www.selse.org/>.<http://www.selse.org/>selse<http://www.selse.org/>.<http://www.selse.org/>org<http://www.selse.org/>)
April 3 - April 4, 2018, Boston, Massachusetts, USA
Important dates:
∙         Abstract submission (mandatory):                      December 20, 2017
∙         Paper submission (for registered abstracts):     January 12, 2018
∙         Authors notification:                                               February 16, 2018
∙         Camera-ready submission:                                    March 1, 2018
The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching especially in safety-critical applications like aerospace and automotive. Growing concern about transient errors, unstable storage cells, and the effects of aging are influencing system and application design. While the computational capabilities of emerging logic and memory device technologies are attractive for several safety-critical applications and new computing philosophies like deep learning become popular, they introduce several reliability challenges that need to be addressed. Additionally, reliability is a key issue for large-scale systems, such as those in data centers and cloud computing infrastructure. This year, we also welcome papers on the system security issues as they relate to and impact system reliability.
The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research directions. SELSE is soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also solicited.
Areas
Key areas of interest are (but not limited to):

  *   Technology trends and their impact on error rates.
  *   New error mitigation techniques.
  *   Error handling protocols (higher-level protocols for robust system design).
  *   Characterizing the overhead and design complexity of error mitigation techniques.
  *   Case studies describing the tradeoff analysis for reliable systems.
  *   System-level models: derating factors and validation of error models.
  *   Experimental data on failures in current and emerging technologies and applications
  *   Characterization of reliability of systems deployed in the field and mitigation of issues.
  *   Software-level impact of hardware failures.
  *   Software frameworks for resilience.
  *   Impact of machine learning components on system resilience.
  *   Resilient accelerator-rich systems.
  *   Inexact or approximate computing as it relates to system errors.
  *   (New) Cross-layer resilience techniques.
  *   (New) System security issues that impact and interact with system reliability.

Submission Guidelines
Additional information and guidelines for submission are available at http<http://www.selse.org/>://<http://www.selse.org/>www<http://www.selse.org/>.<http://www.selse.org/>selse<http://www.selse.org/>.<http://www.selse.org/>org<http://www.selse.org/>.  Submissions and final papers should be in PDF following IEEE two-column transactions format that does not exceed six printed pages of text; the bibliography does not count against this page limit. Papers are not published through IEEE/ACM nor archived in the digital libraries - however, they are distributed to attendees of the workshop. Authors have the option of making their presentation slides available on the SELSE website, but this is not mandatory.
Organizing Committee

General Co-Chairs

Siva Hari, NVIDIA



Laura Monroe, LANL


Program Co-Chairs

Paolo Rech, UFRGS



Karthik Pattabiraman, UBC


Finance Co-Chairs

Laura Monroe, LANL
Steven Raasch, AMD


Publicity Co-Chairs

Michael Sullivan, NVIDIA
Tiago Balen, UFRGS
Stefano Di Carlo, PoliTo
Yi-Pin Fang, TSMC


Documents Chair

Fritz Previlon,
Northeastern University


Industry Liaison

Jon Stephan, Intel


Webmaster

Masab Ahmad, UCONN
Omer Khan, UCONN


Local Arrangements Chair

Devesh Tiwari,
Northeastern University


Advisors to the Committee

Sarah Michalak, LANL
Alan Wood, Oracle
Vilas Sridharan, AMD
Adrian Evans, iRoC




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